
GPIO MUX
30
NS9750B-A1 Datasheet 03/2006
AB3 gpio[46] U 4 I/O 00 Ser port D RTS
01 1284 nAutoFd (host-driven)
02 LCD data bit 22
03 GPIO 46
AA4 gpio[47] U 4 I/O 00 Ser port D CTS
01 1284 nInit (host-driven)
02 LCD data bit 23
03 GPIO 47
AC2 gpio[48] U 2 I/O 00 Timer 14
01 1284 SelectIn (host-driven)
02 DMA ch 2 req
03 GPIO 48
AD1 gpio[49]
1
U 2 I/O 00 Timer 15
01 1284 peripheral logic high (peripheral-driven)
02 DMA ch 2 done
03 GPIO 49
1 This pin is used for bootstrap initialization (see Table 1, “Configuration pins— Bootstrap initialization,”
on page 5). Note that the GPIO pins used as bootstrap pins have a defined powerup state that is
required for the appropriate NS9750B-A1 configuration. If these GPIO pins are also used to control
external devices (for example, power switch enable), the powerup state for the external device should
be compatible with the bootstrap state. If the powerup state is not compatible with the bootstrap
state, either select a different GPIO pin to control the external device or add additional circuitry to
reach the proper powerup state to the external device.
2 gpio[17] is used as both a bootstrap input pin for PLL_ND and an output that controls a power switch for
USB Host power. If the power switch needs to powerup in the inactive state, the enable to the power
switch must be the same value as the bootstrap value for PLL_ND; for example, if PLL_ND requires high on
gpio[17], a high true power switch must be selected. gpio[16] is used for USB_OVR and should have a
noise filter to prevent false indications of overcurrent, unless the USB power IC has this filter built in. See
“Example: Implementing gpio[16] and gpio[17]” on page 31 for an illustration.
3 The nFault signal GPIO6 or GPIO16 can be used as a code-controlled direction pin for the transceiver. The
polarity cannot be altered inside the NS9750B-A1; an inverter will be required.
Pin # Signal name
U/D
OD
(mA)
I/O Descriptions (4 options: 00, 01, 02, 03)
Table 12: GPIO MUX pinout
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