Digi NS9750 Manual do Utilizador descarregar pdf (Página 58)

SRAM timing

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NS9750B-A1 Datasheet 03/2006

Static RAM read cycle configurable wait states

 WTRD = from 1 to 15

WOEN = from 0 to 15

 If the PB field is set to 1, all four byte_lane signals will go low for 32-bit, 16-bit, and 8-bit

read cycles.

 If the PB field is set to 0, the byte_lane signal will always be high.

 The length of the read cycle is determined by the WTRD field.

Note: The length of the st_cs_n, oe_n, and the byte_lane signals are determined by a

combination of the WTRD and the WOEN fields.

Static RAM sequential write cycles

 WTWR = 0

WWEN = 0

 During a 32-bit transfer, all four byte_lane signals will go low.

 During a 16-bit transfer, two byte_lane signals will go low.

 During an 8-bit transfer, only one byte_lane signal will go low.

Note: If the PB field is set to 0, the byte_lane signals will function as write enable signals and the

we_n signal will always be high.

M24M23

M28M27

M20M19

M18M17

M26

M25

Note-1

clk_out<3:0>

data<31:0>

addr<27:0>

st_cs_n<3:0>

oe_n

byte_lane<3:0>

M22M21

M24M23

M22M21

M20M19

M18M17

M16M15

Note1

clk_out<3:0>

data<31:0>

addr<27:0>

st_cs_n<3:0>

we_n

byte_lane<3:0>

byte_lane[3:0] as WE*

1 2 ... 53 54 55 56 57 58 59 60 61 62 63 ... 87 88

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