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SPI timing

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Notes:

1 Active level of SPI enable is inverted (that is, 1) if the CSPOL bit in Serial Channel B/A/C/D Control

value of 0 (low enable) is valid; the SPI slave is fixed to an active low chip select.

2 SPI data order is reversed (that is, LSB last and MSB first) if the BITORDR bit in Serial Channel B/A/C/D

Control Register B (see the NS9750B-A1 Hardware Reference) is set to 0.

3 T

BCLK

is period of BBus clock.

4 ±5% duty cycle skew.

5 ±10% duty cycle skew.

6 C

load

= 10pf for all outputs.

7 SPI data order can be reversed such that LSB is first. Use the BITORDR bit in Serial Channel B/A/C/D Control

SPI master mode 0 and 1: 2-byte transfer (see note 7)

SPI master mode 2 and 3: 2-byte transfer (see note 7)

SP23 SPI enable low hold from last SPI CLK in

rising

15 ns 1, 2 1

SP24 SPI CLK in high time SP26*40% SP26*60% ns 0, 1, 2, 3 5

SP25 SPI CLK in low time SP26*40% SP26*60% ns 0, 1, 2, 3 5

SP26 SPI CLK in period T

BCLK

*10 ns 0, 1, 2, 3

Parm Description Min Max Unit Modes Notes

Table 34: SPI timing parameters

MSB LSB MSB LSB

SP6SP4

SP8SP7

S10SP5SP1

S9SP12SP12

SP11SP11

SP13SP13SP3SP0

SPI CLK Out (Mode 0)

SPI CLK Out (Mode 1)

SPI Enable

SPI Data Out

SPI Data In

MSB LSB MSB LSB

SP6SP4

SP8SP7

S10SP5SP1

S9SP3SP0

SPI CLK Out (Mode 2)

SPI CLK Out (Mode 3)

SPI Enable

SPI Data Out

SPI Data In

1 2 ... 70 71 72 73 74 75 76 77 78 79 80 ... 87 88

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